Event Type:
MSE Grad Presentation
Date
Talk Title:
Design and Demonstration of Mechanical and Electrical reliability of 1µm Redistribution Layers
Location:
Via Teams Video Conferencing 
https://teams.microsoft.com/l/meetup-join/19%3ameeting_YjQ1N2NkNGUtMmE5MC00MDli…

Committee Members: 

Prof. Rao Tummala, Advisor, ECE/MSE 

Prof. Madhavan Swaminathan, ECE/MSE 

Prof. C. P. Wong, MSE 

Dr. Mohanalingam Kathaperumal, ECE 

Leonel Arana, Ph.D., Intel corp. 


Design and Demonstration of Mechanical and Electrical reliability of 1µm Redistribution Layers

Abstract: 

Transistor performance improvement from node to node has slowed down considerably in recent years. The demand for higher computational power, however, is more than ever, especially for applications such as artificial intelligence (AI). To keep up with this ever-increasing demand for higher computational power, new ways are being explored, including the concept of ‘Moore’s Law for Packaging or Interconnections’ by Prof. Tummala. In this concept, the focus is on achieving higher total performance between transistors and interconnects by combining the best of Moore’s law for ICs with Moore’s law for interconnections.  Integration of multiple smaller chips with higher transistor density, together with higher interconnect density, are gaining importance in high-performance computing (HPC) applications. Higher bandwidth requiring higher density of interconnections between two or more chips is, therefore, critical for achieving superior computing performance.

One way of achieving higher bandwidth is by increasing the inputs and outputs (IO) density of package redistribution layers (RDL). The pace of package RDL scaling has not been as aggressive as transistor-scaling over the years. Therefore, there exists a large gap between the IO densities at package and back-end RDL levels. The goal of this thesis is to address this issue by building a reliable and high-bandwidth package RDL with minimum conductor linewidth and spacing (L/S) of 1 µm and ultra-low-k dielectrics. This will lead to a five-fold increase in the package RDL IO density and bandwidth density over the current state-of-the-art.

Several issues associated with design, materials, processes and reliability have been evaluated and addressed in this research. 1 µm RDL L/S with 3.3 aspect ratio were demonstrated with novel materials and process development for zero side-etching of Cu traces. Novel microvia processing technique was developed to build a multilayer structure using ULK dielectrics. Mechanical and electrical reliability are also critical at finer RDL dimensions. Fundamental studies of metal-polymer interactions were performed to enhance adhesion reliability. Thermal cycling reliability was demonstrated for multilayer RDL test vehicle with 4 µm via diameter. Electrical reliability of 1 µm conductor spacings was evaluated for various ULK dielectrics. These advances enable the most advanced polymer RDL technology with bandwidth densities upwards of 5 Tbps/mm.